The present invention relates generally to electronic circuitry, and more particularly to storage devices.
Memory circuits are vital components in computer and electronic systems that require permanent or temporary data storage. The memory circuits, such as dynamic random access memory (DRAM), are used in computer systems, such as processor systems.
In processor based systems and electronic systems, the system operates at a certain frequency. Ideally, memory devices would operate at the same speed as the system. However, memory devices do not generally operate at the same speed as the system. This is due to the high cost involved in manufacturing and operating memory devices that can operate at very high frequencies. Memory devices generally operate at a fraction of the speed of the processor and cause the system to run more slowly.
Memory devices have been unable to operate at the speed of microprocessors because of how they operate. Memory devices have to be very compact to hold and access the large amounts of data they are required to hold. For these devices to operate faster, a significant cost must be incurred to design and produce these devices. Generally, the cost prohibits the inclusion of faster memory devices in these systems.
In these computer and electronic systems, operational speeds of dynamic random access memories used as main memories have been increased, but are still low compared with operation speeds of microprocessors. This relatively low speed increases wait time of the microprocessor and impedes fast processing, as access time and cycle time of the DRAM form a bottleneck in the performance of the whole system.
One way in which memory circuits can be made to write and read data faster is to build the memory circuits so they operate at a higher clock frequency. This has been done in microprocessors, as can be seen by the increase in operating frequency in microprocessors. For example, a microprocessor running at 200 MHZ is generally much faster than one running at 50 MHZ. However, by operating circuits at higher operating frequencies, additional problems are encountered. For example, the amount of heat produced and power used by a circuit operating at a higher frequency can be greatly increased. This corresponds to high cost solutions to handle the heat and power problems. Furthermore, the increased use of portable devices, such as laptop computers, requires that power use by circuits be reduced. Also, the higher operating frequency can cause the integrated circuit die to be more expensive.
Because memory devices are used in many different systems, increasing the speed of memory devices without significantly increasing the cost of memory devices can allow everything from word processors to automatic teller machines to perform tasks more quickly. One way to increase the speed of memory devices is to use both rising and falling edges of a clock signal to trigger data transfers. Typical edge-triggered flip-flops have one clock input that is sensitive to either rising or falling transitions of a clock signal only, depending on the configuration of the particular flip-flop as set by the manufacturer. By using both rising and falling edges, data transfer speeds can be significantly improved, e.g., doubled.
Double-edge triggered designs, however, generally suffer from a number of limitations. For example, the number of transistors involved in implementing each flip-flop is increased substantially. In addition, some double-edge triggered flip-flops suffer from metastability problems and slow response time. Further, double-edge triggered flip-flops may malfunction when the output is applied to precharge dynamic circuits.
FIG. 1 depicts a conventional double-edge triggered D-type flip-flop 100, more fully described in A. Gago et al., xe2x80x9cReduced Implementation of D-Type DET Flip-Flops,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, March 1993, pp. 400-402. In the arrangement depicted in FIG. 1, cross-coupled inverters are used to implement the double-edge triggered flip-flop 100. In these inverters, a clock signal CLK and an inverted clock signal CLKxe2x80x2 drive center transistors 102, while outer transistors 104 are driven by a data signal D. As a result, to generate the output Q, current must be pulled through an outer transistor 104, a center transistor 102, and an output stage 106. This results in unnecessary delays in obtaining the output.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, a need continues to exist for storage devices to which data can be transferred at faster rates.
The above-mentioned and other deficiencies are addressed in the following detailed description. According to one embodiment of the present invention, a double-edge triggered storage device includes an enabled module having center transistors coupled to receive a data input signal. An output module has center transistors that are coupled to receive a normal or inverted clock signal and outer transistors that are coupled to outputs of the enabled module.
Another embodiment is directed to a double-edge triggered storage device that includes cross-coupled enabled inverters and cross-coupled tri-state inverters. Each enabled inverter is formed by center transistors and outer transistors. The center transistors are coupled to receive a data input signal. They generate output signals in response to the data input signal. The outer transistors are coupled to the normal and inverted clock signals. Each tri-state inverter is formed by center transistors and outer transistors. The center transistors receive the output of the enabled inverters. The outer transistors receive the normal and inverted clock signals.
In yet another embodiment, the double-edge triggered storage device also includes a set transistor arrangement that forces the output to a set state, independently of the clock signal, when a set input signal is asserted. Similarly, a reset transistor arrangement forces the output to a reset state, independently of the clock signal, when a reset input signal is asserted. Weak feedback inverters are coupled to outputs of the enabled inverters to maintain the storage device in a logic state in the absence of the clock signal.
Still other implementations include registers, static random access memory (SRAM) devices, integrated circuit (IC) packages, and information-handling systems incorporating such double-edge triggered storage devices. Other advantages of the present invention will be apparent to one skilled in the art upon examining the detailed description and the accompanying drawings.